/*
 * Copyright (c) 2006-2020, YICHIP Development Team
 * @file     g_psram.c
 * @brief    This file contains all the functions prototypes for the psram firmware library.
 *
 * Change Logs:
 * Date            Author             Version        Notes
 * 2021-05-19      dengzhiqian        V1.0.0         the first version  
 */

#include "g_psram.h"

unsigned char FLAG_QUAD = 0;

#if 0
static void psram_set_line_seq(unsigned char val){
	unsigned int tmp;
	tmp = PSRAM_CTRL_REG; 
	tmp &= ~(0x01 << 25);//clear bit[25]
	tmp |= (val << 25);
	PSRAM_CTRL_REG = tmp; 
}

static unsigned char psram_get_task_max(void){
	unsigned int tmp;
	tmp = PSRAM_CTRL_REG; 
    tmp = (tmp >> 20) & 0x07;//bit[22:20]
	return tmp; 
}

static void psram_task_load(void){
	unsigned int tmp;
    unsigned char val = 0x01;
	tmp = PSRAM_CTRL_REG; 
	tmp &= ~(0x01 << 16);//clear bit[16]
	tmp |= (val << 16);
	PSRAM_CTRL_REG = tmp; 
}

static void psram_task_remove(void){
	unsigned int tmp;
    unsigned char val = 0x01;
	tmp = PSRAM_CTRL_REG; 
	tmp &= ~(0x01 << 18);//clear bit[18]
	tmp |= (val << 18);
	PSRAM_CTRL_REG = tmp; 
}
#endif

static void psram_set_task_max(unsigned char val){
	unsigned int tmp;
	tmp = PSRAM_CTRL_REG; 
	tmp &= ~(0x07 << 20);//clear bit[22:20]
	tmp |= (val << 20);
	PSRAM_CTRL_REG = tmp; 
}

static void psram_set_dma_enable(unsigned char val){
	unsigned int tmp;
	tmp = PSRAM_CTRL_REG; 
	tmp &= ~(0x01 << 19);//clear bit[19]
	tmp |= (val << 19);
	PSRAM_CTRL_REG = tmp; 
}

static void psram_task_add(void){
	unsigned int tmp;
    unsigned char val = 0x01;
	tmp = PSRAM_CTRL_REG; 
	tmp &= ~(0x01 << 17);//clear bit[17]
	tmp |= (val << 17);
	PSRAM_CTRL_REG = tmp; 
}

static void psram_set_task_value(unsigned char val){
	unsigned int tmp;
	tmp = PSRAM_CTRL_REG; 
	tmp &= ~(0xff << 8);//clear bit[15:8]
	tmp |= (val << 8);
	PSRAM_CTRL_REG = tmp; 
}

static void psram_set_task_table_addr(unsigned int addr){
	unsigned int tmp;
	tmp = addr & 0xffffff;
	PSRAM_TASK_TABLE_ADDR_REG = tmp; 
}

#if 0
static unsigned char psram_get_task_list(void){
	unsigned int tmp;
	tmp = PSRAM_CTRL_REG; 
    tmp = (tmp >> 0) & 0xff;//bit[7:0]
	return tmp; 
}

static void psram_set_task7_trig_src(unsigned char val){
	unsigned int tmp;
	tmp = PSRAM_TASK_TRIG_SRC_REG; 
	tmp &= ~((unsigned int)0xf << 28);//clear bit[31:28]
	tmp |= (val << 28);
	PSRAM_TASK_TRIG_SRC_REG = tmp; 
}

static void psram_set_task6_trig_src(unsigned char val){
	unsigned int tmp;
	tmp = PSRAM_TASK_TRIG_SRC_REG; 
	tmp &= ~((unsigned int)0xf << 24);//clear bit[27:24]
	tmp |= (val << 24);
	PSRAM_TASK_TRIG_SRC_REG = tmp; 
}

static void psram_set_task5_trig_src(unsigned char val){
	unsigned int tmp;
	tmp = PSRAM_TASK_TRIG_SRC_REG; 
	tmp &= ~(0xf << 20);//clear bit[23:20]
	tmp |= (val << 20);
	PSRAM_TASK_TRIG_SRC_REG = tmp; 
}

static void psram_set_task4_trig_src(unsigned char val){
	unsigned int tmp;
	tmp = PSRAM_TASK_TRIG_SRC_REG; 
	tmp &= ~(0xf << 16);//clear bit[19:16]
	tmp |= (val << 16);
	PSRAM_TASK_TRIG_SRC_REG = tmp; 
}

static void psram_set_task3_trig_src(unsigned char val){
	unsigned int tmp;
	tmp = PSRAM_TASK_TRIG_SRC_REG; 
	tmp &= ~(0xf << 12);//clear bit[15:12]
	tmp |= (val << 12);
	PSRAM_TASK_TRIG_SRC_REG = tmp; 
}

static void psram_set_task2_trig_src(unsigned char val){
	unsigned int tmp;
	tmp = PSRAM_TASK_TRIG_SRC_REG; 
	tmp &= ~(0xf << 8);//clear bit[11:8]
	tmp |= (val << 8);
	PSRAM_TASK_TRIG_SRC_REG = tmp; 
}

static void psram_set_task1_trig_src(unsigned char val){
	unsigned int tmp;
	tmp = PSRAM_TASK_TRIG_SRC_REG; 
	tmp &= ~(0xff << 0);//clear bit[7:0]
	tmp |= (val << 0);
	PSRAM_TASK_TRIG_SRC_REG = tmp; 
}

static void psram_set_task0_trig_src(unsigned char val){
	unsigned int tmp;
	tmp = PSRAM_TASK_TRIG_SRC_REG; 
	tmp &= ~((unsigned int)0xf << 28);//clear bit[31:28]
	tmp |= (val << 28);
	PSRAM_TASK_TRIG_SRC_REG = tmp; 
}
#endif

static void psram_set_irq_clear(unsigned char val){
	unsigned int tmp;
	tmp = PSRAM_IRQ_CTRL_REG; 
	tmp &= ~(0xff << 16);//clear bit[23:16]
	tmp |= (val << 16);
	PSRAM_IRQ_CTRL_REG = tmp; 
}

static void psram_set_irq_enable(unsigned char val){
	unsigned int tmp;
	tmp = PSRAM_IRQ_CTRL_REG; 
	tmp &= ~(0xff << 8);//clear bit[15:8]
	tmp |= (val << 8);
	PSRAM_IRQ_CTRL_REG = tmp; 
}

static unsigned char psram_get_irq_status(void){
	unsigned int tmp;
	tmp = PSRAM_IRQ_CTRL_REG; 
    tmp = (tmp >> 0) & 0xff;//bit[7:0]
	return tmp; 
}

static unsigned int task_conf_table[4*8];

#if 0
static void PSRAM_TaskConfig( G_PSRAM_TaskTypeDef * PSRAM_TaskStruct) {
    PSRAM_TaskStruct->QspiTransferLen                   = 0;
    PSRAM_TaskStruct->SckHiDiv                          = 0;
    PSRAM_TaskStruct->SckLoDiv                          = 0;
    PSRAM_TaskStruct->SingleLineIOMode                  = 0;
    PSRAM_TaskStruct->TransferDir                       = 0;
    PSRAM_TaskStruct->DataPhaseWidth                    = 0;
    PSRAM_TaskStruct->WaitCycle                         = 0;
    PSRAM_TaskStruct->AddrPhaseWidth                    = 0;
    PSRAM_TaskStruct->CmdOnly                           = 0;
    PSRAM_TaskStruct->CmdPhaseWidth                     = 0;
    PSRAM_TaskStruct->QspiCmd                           = 0;
    PSRAM_TaskStruct->QspiAddr                          = 0;
    PSRAM_TaskStruct->DmaLen                            = 0;
    PSRAM_TaskStruct->DmaSaddr                          = 0;
    PSRAM_TaskStruct->DmaFixedAddr                      = 0;
    PSRAM_TaskStruct->ChainTaskAddr                     = 0;
    PSRAM_TaskStruct->ChainEnable                       = 0; 
}
#endif

static void PSRAM_TaskInit(G_PSRAM_TaskTypeDef * PSRAM_TaskStruct, unsigned int* task_table_saddr) {
    // TaskCfg0
    *((unsigned int*)(task_table_saddr + (PSRAM_TaskStruct->TaskIndex)*4 + 0)) =
			(((PSRAM_TaskStruct->QspiTransferLen & 0x7fff) - 1)	<< 17) |\
			(((PSRAM_TaskStruct->SckHiDiv & 0x03) - 1)		<< 15) |\
			(((PSRAM_TaskStruct->SckLoDiv & 0x03) - 1)		<< 13) |\
			((PSRAM_TaskStruct->SingleLineIOMode & 0x01)	<< 12) |\
			((PSRAM_TaskStruct->TransferDir & 0x01)			<< 11) |\
			((PSRAM_TaskStruct->DataPhaseWidth & 0x03)		<< 9) |\
			((PSRAM_TaskStruct->WaitCycle & 0x0f)			<< 5) |\
			((PSRAM_TaskStruct->AddrPhaseWidth & 0x03)		<< 3) |\
			((PSRAM_TaskStruct->CmdOnly & 0x01)				<< 2) |\
			((PSRAM_TaskStruct->CmdPhaseWidth & 0x03)		<< 0);
    // TaskCfg1
    *((unsigned int*)(task_table_saddr + (PSRAM_TaskStruct->TaskIndex)*4 + 1)) = 
			((PSRAM_TaskStruct->QspiCmd & 0xff)				<< 24) |\
			((PSRAM_TaskStruct->QspiAddr & 0xffffff)		<< 0);
    // TaskCfg2
    *((unsigned int*)(task_table_saddr + (PSRAM_TaskStruct->TaskIndex)*4 + 2)) = 
			((PSRAM_TaskStruct->DmaLen & 0xff)						<< 24) |\
			((PSRAM_TaskStruct->DmaSaddr & 0xffffc)					<< 4) |\
			(((PSRAM_TaskStruct->QspiTransferLen & 0x38000) >> 15)	<< 3) |\
			((PSRAM_TaskStruct->DmaFixedAddr & 0x01)				<< 0);
    // TaskCfg3
    *((unsigned int*)(task_table_saddr + (PSRAM_TaskStruct->TaskIndex)*4 + 3)) = 
			(((PSRAM_TaskStruct->DmaLen >> 8) & 0xff)		<< 24) |\
			((PSRAM_TaskStruct->ChainTaskAddr & 0xffffc)	<< 4) |\
			((PSRAM_TaskStruct->ChainEnable & 0x01)			<< 0);
	psram_set_task_table_addr((unsigned int)task_table_saddr);
}

static void PSRAM_Read(unsigned char TASKx, unsigned char qspicmd, unsigned int qspiaddr, unsigned int qspilen, unsigned int dmasaddr, unsigned int dmalen){
	G_PSRAM_TaskTypeDef PSRAM_TaskStruct;

	PSRAM_TaskStruct.TaskIndex				= TASKx;
    PSRAM_TaskStruct.QspiTransferLen		= qspilen;
    PSRAM_TaskStruct.SckHiDiv				= SCK_HIGH_DIV;
    PSRAM_TaskStruct.SckLoDiv 				= SCK_LOW_DIV;
    PSRAM_TaskStruct.SingleLineIOMode		= SINGLE_LINE_DI_AND_DO_MODE;
    PSRAM_TaskStruct.TransferDir			= TRANSFER_DIR_READ_PSRAM;
    PSRAM_TaskStruct.CmdOnly 				= CDM_AND_DATA;
    PSRAM_TaskStruct.QspiCmd				= qspicmd;
    PSRAM_TaskStruct.QspiAddr				= qspiaddr;
    PSRAM_TaskStruct.DmaLen					= dmalen;
    PSRAM_TaskStruct.DmaSaddr				= dmasaddr;
	PSRAM_TaskStruct.DmaFixedAddr          	= 0;
	PSRAM_TaskStruct.ChainTaskAddr         	= 0;
	PSRAM_TaskStruct.ChainEnable           	= 0;

	if(FLAG_QUAD){		
		PSRAM_TaskStruct.CmdPhaseWidth		= CDM_WIDTH_4_BIT;
		switch (qspicmd)
		{
			case PSRAM_Fast_Read_Cmd:
				#ifdef DEBUG_PRINTF
					MyPrintf("PSRAM_Fast_Read!\n");
				#endif
				PSRAM_TaskStruct.DataPhaseWidth	= DATA_WIDTH_4_BIT;
				PSRAM_TaskStruct.WaitCycle 		= 4;
				PSRAM_TaskStruct.AddrPhaseWidth	= ADDR_WIDTH_4_BIT;
				break;
			case PSRAM_Fast_Read_Quad_Cmd:
				#ifdef DEBUG_PRINTF
					MyPrintf("PSRAM_Fast_Read_Quad!\n");
				#endif
				PSRAM_TaskStruct.DataPhaseWidth	= DATA_WIDTH_4_BIT;
				PSRAM_TaskStruct.WaitCycle 		= 6;
				PSRAM_TaskStruct.AddrPhaseWidth	= ADDR_WIDTH_4_BIT;
				break;
			case PSRAM_Wrapped_Read_Cmd:
				#ifdef DEBUG_PRINTF
					MyPrintf("PSRAM_Wrapped_Read!\n");
				#endif
				PSRAM_TaskStruct.DataPhaseWidth	= DATA_WIDTH_4_BIT;
				PSRAM_TaskStruct.WaitCycle 		= 6;
				PSRAM_TaskStruct.AddrPhaseWidth	= ADDR_WIDTH_4_BIT;
				break;
			case PSRAM_Mode_Register_Read_Cmd:
				#ifdef DEBUG_PRINTF
					MyPrintf("PSRAM_Mode_Register_Read!\n");
				#endif
				PSRAM_TaskStruct.DataPhaseWidth	= DATA_WIDTH_4_BIT;
				PSRAM_TaskStruct.WaitCycle 		= 6;
				PSRAM_TaskStruct.AddrPhaseWidth	= ADDR_WIDTH_4_BIT;
				break;
			default: 
				break;
		}
	}
	else{
		PSRAM_TaskStruct.CmdPhaseWidth		= CDM_WIDTH_1_BIT;
		switch (qspicmd)
		{
			case PSRAM_Read_Cmd:
				#ifdef DEBUG_PRINTF
					MyPrintf("PSRAM_Read!\n");
				#endif
				PSRAM_TaskStruct.DataPhaseWidth	= DATA_WIDTH_1_BIT;
				PSRAM_TaskStruct.WaitCycle 		= 0;
				PSRAM_TaskStruct.AddrPhaseWidth	= ADDR_WIDTH_1_BIT;
				break;
			case PSRAM_Fast_Read_Cmd:
				#ifdef DEBUG_PRINTF
					MyPrintf("PSRAM_Fast_Read!\n");
				#endif
				PSRAM_TaskStruct.DataPhaseWidth	= DATA_WIDTH_1_BIT;
				PSRAM_TaskStruct.WaitCycle 		= 8;
				PSRAM_TaskStruct.AddrPhaseWidth	= ADDR_WIDTH_1_BIT;
				break;
			case PSRAM_Fast_Read_Quad_Cmd:
				#ifdef DEBUG_PRINTF
					MyPrintf("PSRAM_Fast_Read_Quad!\n");
				#endif
				PSRAM_TaskStruct.DataPhaseWidth	= DATA_WIDTH_4_BIT;
				PSRAM_TaskStruct.WaitCycle 		= 6;
				PSRAM_TaskStruct.AddrPhaseWidth	= ADDR_WIDTH_4_BIT;
				break;
			case PSRAM_Wrapped_Read_Cmd:
				#ifdef DEBUG_PRINTF
					MyPrintf("PSRAM_Wrapped_Read!\n");
				#endif
				PSRAM_TaskStruct.DataPhaseWidth	= DATA_WIDTH_1_BIT;
				PSRAM_TaskStruct.WaitCycle 		= 8;
				PSRAM_TaskStruct.AddrPhaseWidth	= ADDR_WIDTH_1_BIT;
				break;
			case PSRAM_Mode_Register_Read_Cmd:
				#ifdef DEBUG_PRINTF
					MyPrintf("PSRAM_Mode_Register_Read!\n");
				#endif
				PSRAM_TaskStruct.DataPhaseWidth	= DATA_WIDTH_1_BIT;
				PSRAM_TaskStruct.WaitCycle 		= 8;
				PSRAM_TaskStruct.AddrPhaseWidth	= ADDR_WIDTH_1_BIT;
				break;
			case PSRAM_Read_ID_Cmd:
				#ifdef DEBUG_PRINTF
					MyPrintf("PSRAM_Read_ID!\n");
				#endif
				PSRAM_TaskStruct.DataPhaseWidth	= DATA_WIDTH_1_BIT;
				PSRAM_TaskStruct.WaitCycle 		= 0;
				PSRAM_TaskStruct.AddrPhaseWidth	= ADDR_WIDTH_1_BIT;
				break;
			default: 
				break;
		}

	}	
	PSRAM_TaskInit(&PSRAM_TaskStruct, task_conf_table);
}

static void PSRAM_Write(unsigned char TASKx, unsigned char qspicmd, unsigned int qspiaddr, unsigned int qspilen, unsigned int dmasaddr, unsigned int dmalen){
	G_PSRAM_TaskTypeDef PSRAM_TaskStruct;

	PSRAM_TaskStruct.TaskIndex				= TASKx;
    PSRAM_TaskStruct.QspiTransferLen        = qspilen;
    PSRAM_TaskStruct.SckHiDiv               = SCK_HIGH_DIV;
    PSRAM_TaskStruct.SckLoDiv               = SCK_LOW_DIV;
    PSRAM_TaskStruct.SingleLineIOMode       = SINGLE_LINE_DI_AND_DO_MODE;
    PSRAM_TaskStruct.TransferDir            = TRANSFER_DIR_WRITE_PSRAM;
    PSRAM_TaskStruct.QspiCmd                = qspicmd;
    PSRAM_TaskStruct.QspiAddr               = qspiaddr;
    PSRAM_TaskStruct.DmaLen                 = dmalen;
    PSRAM_TaskStruct.DmaSaddr               = dmasaddr;
	PSRAM_TaskStruct.DmaFixedAddr          	= 0;
	PSRAM_TaskStruct.ChainTaskAddr         	= 0;
	PSRAM_TaskStruct.ChainEnable           	= 0;

	if(FLAG_QUAD)
	{
		PSRAM_TaskStruct.CmdPhaseWidth		= CDM_WIDTH_4_BIT;
		switch (qspicmd)
		{
			case PSRAM_Write_Cmd:
				#ifdef DEBUG_PRINTF
					MyPrintf("PSRAM_Write!\n");
				#endif
				PSRAM_TaskStruct.DataPhaseWidth	= DATA_WIDTH_4_BIT;
				PSRAM_TaskStruct.WaitCycle 		= 0;
				PSRAM_TaskStruct.AddrPhaseWidth	= ADDR_WIDTH_4_BIT;
				PSRAM_TaskStruct.CmdOnly			= CDM_AND_DATA;
				break;
			case PSRAM_Quad_Write_Cmd:
				#ifdef DEBUG_PRINTF
					MyPrintf("PSRAM_Quad_Write!\n");
				#endif
				PSRAM_TaskStruct.DataPhaseWidth	= DATA_WIDTH_4_BIT;
				PSRAM_TaskStruct.WaitCycle 		= 0;
				PSRAM_TaskStruct.AddrPhaseWidth	= ADDR_WIDTH_4_BIT;
				PSRAM_TaskStruct.CmdOnly			= CDM_AND_DATA;
				break;
			case PSRAM_Wrapped_Write_Cmd:
				#ifdef DEBUG_PRINTF
					MyPrintf("PSRAM_Wrapped_Write!\n");
				#endif
				PSRAM_TaskStruct.DataPhaseWidth	= DATA_WIDTH_4_BIT;
				PSRAM_TaskStruct.WaitCycle 		= 0;
				PSRAM_TaskStruct.AddrPhaseWidth	= ADDR_WIDTH_4_BIT;
				PSRAM_TaskStruct.CmdOnly			= CDM_AND_DATA;
				break;
			case PSRAM_Mode_Register_Write_Cmd:
				#ifdef DEBUG_PRINTF
					MyPrintf("PSRAM_Mode_Register_Write!\n");
				#endif
				PSRAM_TaskStruct.DataPhaseWidth	= DATA_WIDTH_4_BIT;
				PSRAM_TaskStruct.WaitCycle 		= 0;
				PSRAM_TaskStruct.AddrPhaseWidth	= ADDR_WIDTH_4_BIT;
				PSRAM_TaskStruct.CmdOnly			= CDM_AND_DATA;
				break;
			case PSRAM_Exit_Quad_Mode_Cmd:
				#ifdef DEBUG_PRINTF
					MyPrintf("PSRAM_Exit_Quad_Mode!\n");
				#endif
				PSRAM_TaskStruct.CmdOnly			= CDM_ONLY;
				FLAG_QUAD = 0;
				break;
			case PSRAM_Reset_Enable_Cmd:
				#ifdef DEBUG_PRINTF
					MyPrintf("PSRAM_Reset_Enable!\n");
				#endif
				PSRAM_TaskStruct.CmdOnly			= CDM_ONLY;
				break;
			case PSRAM_Reset_Cmd:
				#ifdef DEBUG_PRINTF
					MyPrintf("PSRAM_Reset!\n");
				#endif
				PSRAM_TaskStruct.CmdOnly			= CDM_ONLY;
				break;
			case PSRAM_Burst_Length_Toggle_Cmd:
				#ifdef DEBUG_PRINTF
					MyPrintf("PSRAM_Burst_Length_Toggle!\n");
				#endif
				PSRAM_TaskStruct.CmdOnly			= CDM_ONLY;
				break;
			default: 
				break;
		}
	}
	else{
		PSRAM_TaskStruct.CmdPhaseWidth		= CDM_WIDTH_1_BIT;
		switch (qspicmd)
		{
			case PSRAM_Write_Cmd:
				#ifdef DEBUG_PRINTF
					MyPrintf("PSRAM_Write!\n");
				#endif
				PSRAM_TaskStruct.DataPhaseWidth	= DATA_WIDTH_1_BIT;
				PSRAM_TaskStruct.WaitCycle 		= 0;
				PSRAM_TaskStruct.AddrPhaseWidth	= ADDR_WIDTH_1_BIT;
				PSRAM_TaskStruct.CmdOnly			= CDM_AND_DATA;
				break;
			case PSRAM_Quad_Write_Cmd:
				#ifdef DEBUG_PRINTF
					MyPrintf("PSRAM_Quad_Write!\n");
				#endif
				PSRAM_TaskStruct.DataPhaseWidth	= DATA_WIDTH_4_BIT;
				PSRAM_TaskStruct.WaitCycle 		= 0;
				PSRAM_TaskStruct.AddrPhaseWidth	= ADDR_WIDTH_4_BIT;
				PSRAM_TaskStruct.CmdOnly			= CDM_AND_DATA;
				break;
			case PSRAM_Wrapped_Write_Cmd:
				#ifdef DEBUG_PRINTF
					MyPrintf("PSRAM_Wrapped_Write!\n");
				#endif
				PSRAM_TaskStruct.DataPhaseWidth	= DATA_WIDTH_1_BIT;
				PSRAM_TaskStruct.WaitCycle 		= 0;
				PSRAM_TaskStruct.AddrPhaseWidth	= ADDR_WIDTH_1_BIT;
				PSRAM_TaskStruct.CmdOnly			= CDM_AND_DATA;
				break;
			case PSRAM_Mode_Register_Write_Cmd:
				#ifdef DEBUG_PRINTF
					MyPrintf("PSRAM_Mode_Register_Write!\n");
				#endif
				PSRAM_TaskStruct.DataPhaseWidth	= DATA_WIDTH_1_BIT;
				PSRAM_TaskStruct.WaitCycle 		= 0;
				PSRAM_TaskStruct.AddrPhaseWidth	= ADDR_WIDTH_1_BIT;
				PSRAM_TaskStruct.CmdOnly			= CDM_AND_DATA;
				break;
			case PSRAM_Enter_Quad_Mode_Cmd:
				#ifdef DEBUG_PRINTF
					MyPrintf("PSRAM_Enter_Quad_Mode!\n");
				#endif
				PSRAM_TaskStruct.CmdOnly			= CDM_ONLY;
				FLAG_QUAD = 1;
				break;
			case PSRAM_Reset_Enable_Cmd:
				#ifdef DEBUG_PRINTF
					MyPrintf("PSRAM_Reset_Enable!\n");
				#endif
				PSRAM_TaskStruct.CmdOnly			= CDM_ONLY;
				break;
			case PSRAM_Reset_Cmd:
				#ifdef DEBUG_PRINTF
					MyPrintf("PSRAM_Reset!\n");
				#endif
				PSRAM_TaskStruct.CmdOnly			= CDM_ONLY;
				break;
			case PSRAM_Burst_Length_Toggle_Cmd:
				#ifdef DEBUG_PRINTF
					MyPrintf("PSRAM_Burst_Length_Toggle!\n");
				#endif
				PSRAM_TaskStruct.CmdOnly			= CDM_ONLY;
				break;
			default: 
				break;
		}
	}	
	PSRAM_TaskInit(&PSRAM_TaskStruct, task_conf_table);
}

char G_GET_PSRAM_Status(void)
{
	return psram_get_irq_status();
}

/**
 * @method G_PSRAM_Enable_QUAD
 * @brief  enter quad mode
 * @param  None
 * @retval None
 */
void G_PSRAM_Enable_QUAD(void)
{
	PSRAM_Write(0, PSRAM_Enter_Quad_Mode_Cmd, 0, 0x00, 0, 0x00);
	psram_set_task_max(1);
	psram_set_task_value(TASK0);
	psram_set_irq_clear(TASK0);
	psram_set_irq_clear(0);
	psram_set_irq_enable(TASK0);
	psram_task_add();
	psram_set_dma_enable(PSRAM_DMA_ENABLE);
	while(0x01 !=  psram_get_irq_status());
}

/**
 * @method G_PSRAM_DataWrite
 * @brief  psram write data
 * @param  addr: write addr 
 * @param  len: write len
 * @param  tbuf:  pointer to a buf that contains the data you want write
 * @retval None
 */
void G_PSRAM_DataWrite(unsigned int addr,unsigned int len, unsigned char *tbuf)
{
	PSRAM_Write(0, PSRAM_Quad_Write_Cmd,addr, len, (unsigned int)tbuf, len);
	psram_set_task_max(1);
	psram_set_task_value(TASK0);
	psram_set_irq_clear(TASK0);
	psram_set_irq_clear(0);
	psram_set_irq_enable(TASK0);
	psram_task_add();
	psram_set_dma_enable(PSRAM_DMA_ENABLE);
	while(0x01 !=  psram_get_irq_status());
}

/**
 * @method G_PSRAM_DataRead
 * @brief  psram read data
 * @param  len: read len 
 * @param  rbuf: pointer to a buf that contains the data you want read
 * @retval None
 */
void G_PSRAM_DataRead(unsigned int addr,unsigned int len, unsigned char *rbuf)
{
	PSRAM_Read(0, PSRAM_Fast_Read_Quad_Cmd, addr, len, (unsigned int)rbuf, len);
	psram_set_task_max(1);
	psram_set_task_value(TASK0);
	psram_set_irq_clear(TASK0);
	psram_set_irq_clear(0);
	psram_set_irq_enable(TASK0);
	psram_task_add();
	psram_set_dma_enable(PSRAM_DMA_ENABLE);
	while(0x01 !=  psram_get_irq_status());
}

